{"product_id":"design-of-cost-efficient-interconnect-processing-marcello-coppola-9781420044713","title":"Design of Cost-Efficient Interconnect Processing Units: Spidergon Stnoc","description":"\u003cp\u003e\u003cstrong\u003eStreamlined Design Solutions Specifically for NoC\u003c\/strong\u003e\u003cbr\u003eTo solve critical network-on-chip (NoC) architecture and design problems related to structure, performance and modularity, engineers generally rely on guidance from the abundance of literature about better-understood system-level interconnection networks. However, on-chip networks present several distinct challenges that require novel and specialized solutions not found in the tried-and-true system-level techniques.\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eA Balanced Analysis of NoC Architecture\u003c\/strong\u003e\u003cbr\u003eAs the first detailed description of the commercial Spidergon STNoC architecture, \u003cstrong\u003eDesign of Cost-Efficient Interconnect Processing Units: Spidergon STNoC\u003c\/strong\u003e examines the highly regarded, cost-cutting technology that is set to replace well-known shared bus architectures, such as STBus, for demanding multiprocessor system-on-chip (SoC) applications. Employing a balanced, well-organized structure, simple teaching methods, numerous illustrations, and easy-to-understand examples, the authors explain: \u003c\/p\u003e\u003cul\u003e \u003cp\u003e \u003c\/p\u003e \u003cli\u003ehow the SoC and NoC technology works\u003c\/li\u003e \u003cli\u003ewhy developers designed it the way they did\u003c\/li\u003e \u003cli\u003ethe system-level design methodology and tools used to configure the Spidergon STNoC architecture\u003c\/li\u003e \u003cli\u003edifferences in cost structure between NoCs and system-level networks\u003c\/li\u003e \u003c\/ul\u003e\u003cp\u003eFrom professionals in computer sciences, electrical engineering, and other related fields, to semiconductor vendors and investors - all readers will appreciate the encyclopedic treatment of background NoC information ranging from CMPs to the basics of interconnection networks. The text introduces innovative system-level design methodology and tools for efficient design space exploration and topology selection. It also provides a wealth of key theoretical and practical MPSoC and NoC topics, such as technological deep sub-micron effects, homogeneous and heterogeneous processor architectures, multicore SoC, interconnect processing units, generic NoC components, and embeddings of common communication patterns. \u003c\/p\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eAuthor:\u003c\/b\u003e Marcello Coppola,Miltos D. Grammatikakis,Riccardo Locatelli\u003cbr\u003e\u003cb\u003eISBN-10:\u003c\/b\u003e 1420044710\u003cbr\u003e\u003cb\u003eISBN-13:\u003c\/b\u003e 9781420044713\u003cbr\u003e\u003cb\u003ePublisher:\u003c\/b\u003e CRC Press\u003cbr\u003e\u003cb\u003eLanguage:\u003c\/b\u003e English\u003cbr\u003e\u003cb\u003ePublished:\u003c\/b\u003e 09\/01\/2008\u003cbr\u003e\u003cb\u003ePages:\u003c\/b\u003e 288\u003cbr\u003e\u003cb\u003eFormat:\u003c\/b\u003e Hardcover\u003cbr\u003e\u003cb\u003eWeight:\u003c\/b\u003e 1.45lbs\u003cbr\u003e\u003cb\u003eSize:\u003c\/b\u003e 9.30h x 6.40w x 1.00d\u003cbr\u003e\u003cbr\u003e\u003cb\u003eReview Citation(s): \u003c\/b\u003e\u003cbr\u003e\u003ci\u003eScitech Book News\u003c\/i\u003e 03\/01\/2009 pg. 160","brand":"Marcello Coppola","offers":[{"title":"Hardcover","offer_id":48088195825919,"sku":"9781420044713","price":160.0,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0662\/2982\/9887\/files\/img_1f503358-1129-46bc-81fd-9e0fa5bc2821.jpg?v=1769103588","url":"https:\/\/www.whiterainbookhouse.com\/products\/design-of-cost-efficient-interconnect-processing-marcello-coppola-9781420044713","provider":"WR Book House","version":"1.0","type":"link"}