ASIC Design and Synthesis: Rtl Design Using Verilog by Taraate, Vaibbhav

ASIC Design and Synthesis: Rtl Design Using Verilog (Paperback) (ISBN-13: 9789813346444)

Vendor: Vaibbhav Taraate
Product type: Books
Format: Paperback
$139.99
$139.99
$139.99
Subtotal: $139.99
ASIC Design and Synthesis: Rtl Design Using Verilog by Taraate, Vaibbhav

ASIC Design and Synthesis: Rtl Design Using Verilog

$139.99
ASIC Design and Synthesis: Rtl Design Using Verilog by Taraate, Vaibbhav

ASIC Design and Synthesis: Rtl Design Using Verilog

$139.99
Format: Paperback
Description
Description
x
This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.



Author: Vaibbhav Taraate
ISBN-10: 9813346442
ISBN-13: 9789813346444
Publisher: Springer
Language: English
Published: 01/08/2022
Pages: 330
Format: Paperback
Weight: 1.09lbs
Size: 9.21h x 6.14w x 0.74d
By Vaibbhav Taraate
By Vaibbhav Taraate
x
Vaibbhav Taraate is an entrepreneur and mentor at "1 Rupee S T". He holds B.E. (Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold Medal for standing first in all engineering branches. He completed his M.Tech. (Aerospace Control and Guidance) at the Indian Institute of Technology (IIT) Bombay, India, in 1999. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog, VHDL and SystemVerilog. He has worked with multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis and optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.

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