System-On-Chip Test Architectures: Nanometer Design for Testability Volume . (Hardcover) (ISBN-13: 9780123739735)

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

Author: Laung-Terng Wang,Charles E. Stroud,Nur A. Touba
ISBN-10: 012373973X
ISBN-13: 9780123739735
Publisher: Morgan Kaufmann Publishers
Language: English
Published: 11/01/2007
Pages: 896
Format: Hardcover
Weight: 3.48lbs
Size: 9.25h x 7.66w x 1.60d