Transactions on High-Performance Embedded Architectures and Compilers II (Paperback) (ISBN-13: 9783642009037)

Special Section on High-Performance Embedded Architectures and Compilers.- Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches.- Compiler-Assisted Memory Encryption for Embedded Processors.- Branch Predictor Warmup for Sampled Simulation through Branch History Matching.- Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems.- Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization.- Regular Papers.- Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors.- Fetch Gating Control through Speculative Instruction Window Weighting.- Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers.- Linux Kernel Compaction through Cold Code Swapping.- Complexity Effective Bypass Networks.- A Context-Parameterized Model for Static Analysis of Execution Times.- Reexecution and Selective Reuse in Checkpoint Processors.- Compiler Support for Code Size Reduction Using a Queue-Based Processor.- Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC.- Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories.

Author: Per Stenström
ISBN-10: 3642009034
ISBN-13: 9783642009037
Publisher: Springer
Language: English
Published: 04/22/2009
Pages: 327
Format: Paperback
Weight: 1.15lbs
Size: 9.37h x 6.30w x 0.78d